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BioSys
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BioSys – Hardware Platform for Advanced Image Processing

Scientific goal of the project

The scientific goal of the project was to develop hardware processing platform dedicated for biometric application hardware system designed to analyze iris biometric data. The device is part of the work conducted by the authors on the complete iris identification system (1:N). This specialized architecture was mainly composed of digital signal processors and field-programmable gate arrays.

The essence of the problem

A biometric security system must process computationally intensive tasks of authentication flow, such as quality assessment, segmentation and analysis, protocols, and database scanning. This flow contains two broad areas of computing: mathematical calculations (typical for DSP systems) and data manipulation and testing (typical for standard processor architectures). Even though such systems require a fair amount of signal processing, typical personal computers (PCs) are still widely used for this purpose with software that is responsible for data processing. Moreover, although current commercially available systems use images that originate from relatively simple vision systems, these systems will have to handle more information and increased processing in the near future because recently a significant effort has been focused on authenticating objects at-a-distance and on-the-move using the iris biometric.
The main motivation for this work was to develop a hardware system for iris identification as a positive biometric system that is able to implement contextual and non-contextual filtering, image segmentation, pattern calculation, and testing within a template’s repository. An additional requirement for the device was to impose certain processing time limits, which is important in high-throughput biometric authentication or when preprocessing and biometric sample quality assessment must be conducted using a video signal with a certain frame rate. Thus, the described solution introduces a specialized hardware-based architecture that can take advantage of the inherent parallelism of FPGAs and their embedded processors as well as the contextual filtering of DSPs. Additionally, DSP reconfiguration and multicore processing techniques used for even more efficient data processing have been tested.

Detailed characteristic of final result

The block diagram of the system is presented in Fig. 1. It is worth emphasizing that although the work until now included identification based on the iris, information about other biometric modalities can easily be transferred to the device. Appropriate procedures can then be dynamically implemented in the FPGA and the DSPs to address the given sensor data.

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Fig. 1. The system architecture

The proposed hardware architecture was applied to the biometric application BioServer and consists of two separate physical boards. The first, a Virtex-5 FXT Xilinx ML510 Embedded Development Platform, forms the basis for an embedded system, which is based on two PowerPC 440 microprocessors; the system is called BioSys.

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Fig. 2. BioServer device.

The second one was designed from scratch and is called biometric computation unit (BioCU), and its main components include a Xilinx Spartan 3AN FPGA and four digital signal processors: two of which are fixed-point (CPU0 and CPU1) and two of which are floating-point (FPU0 and FPU1). A picture of the BioServer device is presented in Fig. 2. The BioCU board – separately presented in figure 3, is inserted into one of the PCI 32-bit slots on the ML510 platform—BioSys.

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Fig. 3. BioCU device.

In the presented version of the hardware architecture, the authors decided to use DSP distributed resources to implement all of the iris identification processing according to Fig. 1, including iris segmentation and preprocessing, feature extraction and a 1:N comparator. For typical image processing, the TI C64x+ IMGLIB library was used. FPGA resources are used to support data transfer, to host and manage calculation tasks among DSP units (mainly CP0 and CP1), to configure resources at startup including caching the database in the local DDR memories of CP DSP units and finally, to supervise firmware execution on the DSPs.